Anti-fuse memory is one type of one-time programmable (OTP) memory in which the device can be permanently programmed (electrically) with data once. This data is programmed by an end user for a particular application. There are several types of OTP memory cells which can be used. OTP memories provide users with a level of flexibility since any data can be programmed.
Anti-fuse memory can be utilized in all one time programmable applications, including RF-ID tags. RF-ID tagging applications are gaining more acceptance in the industry, particularly in sales, security, transport, logistics, and military applications for example. The simplicity and full CMOS compatibility anti-fuse memory allows for application of the RF-ID tag concept to integrated circuit manufacturing and testing processes. Therefore, IC manufacturing productivity can be increased by utilizing anti-fuse memory in combination with an RF communication interface on every wafer and/or every die on the wafer allowing for contact-less programming and reading chip specific or wafer specific information during IC manufacturing and packaging, as well as during printed circuit board assembly.
FIG. 1 is a circuit diagram of a known anti-fuse memory cell, while FIGS. 2 and 3 show the planar and cross-sectional views respectively of the anti-fuse memory cell shown in FIG. 1. The anti-fuse memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. Anti-fuse device 12 is considered a gate dielectric breakdown based anti-fuse devices. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer, is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses should be reliable while simple to manufacture with a low cost CMOS process.
FIG. 4a shows a cross-sectional view of an anti-fuse transistor that can be manufactured with any standard CMOS process. This anti-fuse transistor and its variants are disclosed in commonly owned U.S. patent application Ser. No. 10/553,873 filed on Oct. 21, 2005, and commonly owned U.S. patent application Ser. No. 11/762,552 filed on Jun. 13, 2007, the contents of which are incorporated by reference. In the presently shown example, the anti-fuse transistor is almost identical to a simple thick gate oxide, or input/output MOS transistor with one floating diffusion terminal. The disclosed anti-fuse transistor, also termed a split-channel capacitor or a half-transistor, can be reliably programmed such that the fuse link between the polysilicon gate and the substrate can be predictably localized to a particular region of the device. The cross-section view of FIG. 4a is taken along the channel length of the device. The channel is generally understood to be the area underneath an overlying polysilicon gate, having a length defined by edges of the polysilicon gate adjacent respective diffusion regions.
Anti-fuse cell 30 includes a variable thickness gate oxide 32 formed on the substrate channel region 34, a polysilicon gate 36, sidewall spacers 38, a field oxide region 40 a diffusion region 42, and an LDD region 44 in the diffusion region 42. A bitline contact 46 is shown to be in electrical contact with diffusion region 42. The variable thickness gate oxide consists of a thick gate oxide 32 and a thin gate oxide 33 such that a portion of the channel length is covered by the thick gate oxide and the remaining portion of the channel length is covered by the thin gate oxide. Generally, the thin gate oxide is a region where oxide breakdown can occur. The thick gate oxide edge meeting diffusion region 42 on the other hand, defines an access edge where gate oxide breakdown is prevented and current between the gate 36 and diffusion region 42 is to flow for a programmed anti-fuse transistor. While the distance that the thick oxide portion extends into the channel region depends on the mask grade, the thick oxide portion is preferably formed to be at least as long as the minimum length of a high voltage transistor formed on the same chip.
In this example, the diffusion region 42 is connected to a bitline through a bitline contact 46, or other line for sensing a current from the polysilicon gate 36, and can be doped to accommodate programming voltages or currents. This diffusion region 42 is formed proximate to the thick oxide portion of the variable thickness gate oxide. To further protect the edge of anti-fuse cell 30 from high voltage damage, or current leakage, a resistor protection oxide (RPO), also known as a salicide protect oxide, can be introduced during the fabrication process to further space metal particles from the edge of sidewall spacer 38. This RPO is preferably used during the salicidiation process for preventing only a portion of diffusion region 42 and a portion of polysilicon gate 36 from being salicided. It is well known that salicided transistors are known to have higher leakage and therefore lower breakdown voltage. Thus having a non-salicided diffusion region 42 will reduce leakage. Diffusion region 42 can be doped for low voltage transistors or high voltage transistors or a combination of the two resulting in same or different diffusion profiles.
A simplified plan view of the anti-fuse cell 30 is shown in FIG. 4b. Bitline contact 46 can be used as a visual reference point to orient the plan view with the corresponding cross-sectional view of FIG. 4a. The active area 48 is the region of the device where the channel region 34 and diffusion region 42 is formed, which is defined by an OD mask during the fabrication process. The dashed outline 50 defines the areas in which the thick gate oxide is to be formed via an OD2 mask during the fabrication process. More specifically, the area enclosed by the dashed outline 50 designates the regions where thick oxide is to be formed. OD simply refers to an oxide definition mask that is used during the CMOS process for defining the regions on the substrate where the oxide is to be formed, and OD2 refers to a second oxide definition mask different than the first. According to an embodiment of the present invention, the thin gate oxide area bounded by edges of the active area 48 and the rightmost edge of the OD2 mask, is minimized. In the presently shown embodiment, this area can be minimized by shifting the rightmost OD2 mask edge towards the parallel edge of active area 48. Commonly owned U.S. patent application Ser. No. 11/762,552 filed on Jun. 13, 2007, the contents of which are incorporated by reference, describes alternate single transistor anti-fuse memory cells which can be used in a non-volatile memory array.
FIG. 5 is a plan view layout of a single transistor anti-fuse memory cell memory array according to an embodiment of the present invention. In the present example, only four wordlines and four bitlines are shown. Each single transistor anti-fuse cell 30 in memory array 60 has one polysilicon gate 62, and have the same structure as anti-fuse cell 30 of FIGS. 4a and 4b. In memory array 60, the polysilicon line forming polysilicon gates 62 of each anti-fuse memory cell are common to all the anti-fuse memory cells of the row. Memory array 60 is shown to include sixteen anti-fuse memory cells, where four are arranged in each of first row 64, second row 66, third row 68 and fourth row 70. Wordlines WLi, WLi+1, WLi+2 and WLi+3 are connected to the polysilicon gates 62 of rows 64, 66, 68 and 70 respectively. The dashed outlines 72 define the areas in the memory array in which a thick gate oxide is to be formed via a thick gate oxide definition mask during the fabrication process. In the configuration shown in FIG. 5, each pair of memory cells from rows 64 and 66 share a common diffusion region 74 and a common bitline contact 76. Each bitline contact is connected to a different bitline, such as bitlines BLn, BLn+1, BLn+2 and BLn+3. Connected to each of the bitlines is a precharge circuit 78, and a column decoder and sense amplifier circuit block 80. The precharge circuit 78 is responsible for precharging all the bitlines to a predetermined voltage for a read operation, while the column decoder and sense amplifier circuit block 80 includes multiplexing devices for sharing one sense amplifier with one or more bitlines. The actual layout of a memory array using the architecture of FIG. 5 can have the precharge circuit 78 located at one end of the bitlines opposite to the column decoder and sense amplifier circuit block 80, or adjacent or integrated with the column decoder and sense amplifier circuit block 80.
An overview of the program and read operations is now discussed with reference to the anti-fuse cell 30 of FIGS. 4a and 4b, and memory array 60 of FIG. 5. Generally, the anti-fuse transistors are programmed by rupturing the gate oxide, preferably at one of the thin/thick gate oxide boundary and the thin gate oxide/source diffusion edge. This is accomplished by applying a high enough voltage differential between the gate and the channel of the cells to be programmed and a substantially lower voltage differential, if any, on all other cells. Therefore, once a permanent conductive link is formed, a current applied to the polysilicon gate will flow through the link and the channel to the diffusion region, which can be sensed by conventional sense amplifier circuits. In the present example, programming of anti-fuse cell 30 is achieved by grounding selected bitlines to 0V, and driving a selected row to a programming voltage level (VPP) that is typically greater than the VDD voltage supply provided to other circuits. Under these conditions, the thin gate oxide 33 is intended to breakdown in the presence of the large electrical field formed between the channel region 34 and the wordline, thereby creating an electrically conductive connection between channel region 34 and polysilicon gate 36. This electrically conductive connection can be referred to as a conductive link or anti-fuse. In FIG. 5 for example, if BLn is grounded and WLi is selected to be driven to VPP, then the anti-fuse cell 30 at the intersection of BLn and WLi will be programmed once its conductive link is formed. Hence any anti-fuse transistor connected to WLi can be programmed if its corresponding bitline is grounded. On the other hand, inhibiting programming of any anti-fuse transistor connected to WLi is done by biasing the bitlines connected to them to VDD. The reduced electric field is insufficient for the conductive link to be formed.
To read a programmed or unprogrammed anti-fuse transistor with a formed conductive link, all the bitlines are precharged to VSS followed by driving a selected wordline to VDD. Any programmed anti-fuse transistor having a conductive link will drive its corresponding bitline to VDD through its VDD driven wordline via the conductive link. The increased bitline voltage can then be sensed. Any unprogrammed anti-fuse transistor having an absence of a conductive link will have no effect on its corresponding bitline, which means that it remains at the VSS precharge level.
It should be appreciated by those skilled in the art that OTP memories are programmed by the end customer, not by the manufacturer or the vendor. Accordingly, there should be some qualification provided by the manufacturer that the provided OTP memories have been tested to operate properly before use by the end customer. More specifically, the manufacturer should qualify that the circuits of the OTP memory function properly. Defective cells can be replaced with extra rows or columns of cells after unsuccessful programming by the end user, using well known redundancy techniques. In particular, this testing should ensure that fabricated circuits such as the row decoders and column decoders function as designed, and that there are no manufacturing defects during formation of wordlines and bitlines.
It is difficult to test the functionality of the previously described OTP memory device because the bitlines are precharged to a voltage level that corresponds to that of an unprogrammed cell, and driving wordlines to a read voltage will have no effect as the cells are unprogrammed. For the described OTP memory device, the bitlines will rise towards VDD only when a programmed OTP memory cell is activated.
It is, therefore, desirable to provide circuits for testing an unprogrammed OTP memory array, without programming any of the OTP memory cells.